v0.2.1
Fast, portable C library for geometry input/output
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endian.h
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1 /****************************************************************************
2 ** gmio
3 ** Copyright Fougue (24 Jun. 2016)
4 ** contact@fougue.pro
5 **
6 ** This software is a reusable library whose purpose is to provide complete
7 ** I/O support for various CAD file formats (eg. STL)
8 **
9 ** This software is governed by the CeCILL-B license under French law and
10 ** abiding by the rules of distribution of free software. You can use,
11 ** modify and/ or redistribute the software under the terms of the CeCILL-B
12 ** license as circulated by CEA, CNRS and INRIA at the following URL
13 ** "http://www.cecill.info/licences/Licence_CeCILL-B_V1-en.html".
14 ****************************************************************************/
15 
23 #ifndef GMIO_ENDIAN_H
24 #define GMIO_ENDIAN_H
25 
26 #include "global.h"
27 
30 {
33 
37 
41 
42 #ifdef GMIO_HOST_IS_BIG_ENDIAN
44 #else
45 
51  GMIO_ENDIANNESS_HOST = GMIO_ENDIANNESS_LITTLE
52 #endif
53 };
54 
56 
59 
61 
62 #endif /* GMIO_ENDIAN_H */
63 
#define GMIO_API
Expands either to GMIO_DECL_EXPORT or GMIO_DECL_IMPORT when respectively compiling/using the DLL...
Definition: global.h:76
The least significant byte is stored at the lowest address.
Definition: endian.h:36
Fundamental global declarations, included by almost all other header/source files.
#define GMIO_C_LINKAGE_BEGIN
Expands to extern "C" { when building with a C++ compiler.
Definition: global.h:181
gmio_endianness
This enum identifies common endianness (byte order) of computer memory.
Definition: endian.h:29
Other (unknown) byte-order.
Definition: endian.h:32
Defines the endianness(byte order) used by the host computer for storing data in memory.
Definition: endian.h:51
#define GMIO_C_LINKAGE_END
Expands to } when building with a C++ compiler.
Definition: global.h:183
The most significant byte is stored at the lowest address.
Definition: endian.h:40
enum gmio_endianness gmio_host_endianness()
Returns endianness (byte order) of the host's CPU architecture.
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